renesas lsis rev.0.1_48a_beez 1 33,554,432 - bit (2,097,152 - word by 16 - bit/4,194,304 - word by 8 - bit) cmos 3.3v - only flash memory & 4,194,304 - bit (262,144 - word by 16 - bit/524,288 - word by 8 - bit) cmos sram stacked - mcp (micro multi chip package) m6mgb/t331s4bkt preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) the m6mgb/t331s4bkt is a stacked micro multi chip package (s - m mcp) that contents 32m - bit flash memory and 4m - bit static ram in a 52 - pin tsop for lead free use. 32m - bit flash memory is a 4,194,304 bytes / 2,097,152 words, 3.3v - only, and high performance non - volatile memory fabricated by cmos technology for the peripheral circuit and dinor (divided bit - line nor) architecture for the memory cell. 4m - bit sram is a 524,288 bytes / 262,144 words asynchronous sram fabricated by silicon - gate cmos technology. m6mgb/t331s4bkt is suitable for the application of the mob ile - communication - system to reduce both the mount space and weight. m6mgb/t331s4bkt provides for software lock release function. usually, all memory blocks are locked and can not be programmed or erased, when f - wp# is low. using software lock release function, program or erase operation can be executed. access time flash 70ns (max.) sram 70ns (max.) supply voltage vcc=2.7 ~ 3.0v ambient temperature ta= - 40 ~ 85 c package 52pin tsop(type - ii), lead pitch 0.4mm outer - lead finishing: sn - cu application outline 52ptj - a mobile communication products description features 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a15 a14 a13 a12 a11 a10 a9 a8 a19 s - ce1# f - rp# f - wp# s - ce2 a20 a18 a17 a7 a6 a5 a4 a3 s - ub# gnd s - lb# dq15/a - 1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 f - vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# gnd 28 27 f - ce# a0 25 26 a2 a1 10.49 mm s - vcc we# a16 m6mgb/t331s4bkt du byte# 10.79 mm f - vcc s - vcc gnd a - 1 - a17 a18 - a20 dq0 - dq15 f - ce# s - ce#,s - ce2 oe# we# : vcc for flash : vcc for sram :gnd for flash/sram :flash/sram common address :address for flash :data i/o :flash chip enable :sram chip enable :flash/sram output enable :flash/sram write enable f - wp# f - rp# f - ry/by# byte# s - lb# s - ub# du : flash write protect :flash reset power down :flash ready/busy :flash/sram byte enable :sram lower byte :sram upper byte :do not use
renesas lsis rev.0.1_48a_beez 2 33,554,432 - bit (2,097,152 - word by 16 - bit/4,194,304 - word by 8 - bit) cmos 3.3v - only flash memory & 4,194,304 - bit (262,144 - word by 16 - bit/524,288 - word by 8 - bit) cmos sram stacked - mcp (micro multi chip package) m6mgb/t331s4bkt preliminary notice: this is not a final specification. some parametric limits are subject to change. capacitance mcp block diagram note 1): in case of x8 organization, a - 1 is added, and only lower byte data(dq0 to dq7) are assigned to i/o and upper byte data(dq8 to dq15) are high - z. note 2): in the flash memory part there are ? vcc ? s which mean ? f - vcc ? . in the sram part there are ? ub# ? and ? lb# ? which mean ? s - ub# ? and ? s - ub# ? , respectively. note 3): ? du(don ? t use) ? pin must be open ,otherwise be inputted within 0v ~ vcc . a0 to a20 a0 to a20 f - wp# f - rp# we# oe# s - ub# s - lb# dq0 to dq15 32 mbit dinor flash memory f - vcc gnd f - ce# 4 mbit sram s - vcc a0 to a17 s - ce1# s - ce2 byte# 1) 1) 1) 1) min. typ. max. cin input capacitance a20-a0, oe#, we#, f-ce#, f-wp#, f-rp#, s-ce1#, s-ce2, byte#, s-lb#, s-ub# 18 pf cout output capacitance dq15-dq0 22 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter
these materials are intended as a reference to assist our custom ers in the selection of the renesas technology corporation product best suited to the customer's ap plication; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage , or infringement of any third - party's rights, originating in the use of any product data, diag rams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents infor mation on products at the time of publication of these materials , and are subject to change by renesas technology corporation without notice due to product improvemen ts or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product informati on before purchasing a product listed herein. the information described here may contain technical inaccuracie s or typographical errors. renesas technology corporation assumes no responsibility for any damage , liability, or other loss rising from these inaccuracies or err ors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page ( http://www.renesas.com ). when using any or all of the information contained in these mate rials, including product data, diagrams, charts, programs, and a lgorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage , liability or other loss resulting from the information contain ed herein. renesas technology corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. please conta ct renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, su ch as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese ex port control restrictions, they must be exported under a license from the japanese government and cannot be imported into a coun try other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan an d/or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials o r the products contained therein. renesas technology corporation puts the maximum effort into making semi conductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage.remember to give due co nsideration to safety when making your circuit designs, with app ropriate measures such as (i) placement of substitutive, auxilia ry circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials keep safety first in your circuit designs! rej03c0157 ? 2003 renesas technology corp. new publication, effective april 2003. specifications subject to change without notice nippon bldg.,6 - 2, otemachi 2 - chome, chiyoda - ku ,tokyo,100 - 0004 japan renesas lsis 33,554,432 - bit (2,097,152 - word by 16 - bit/4,194,304 - word by 8 - bit) cmos 3.3v - only flash memory & 4,194,304 - bit (262,144 - word by 16 - bit/524,288 - word by 8 - bit) cmos sram stacked - mcp (micro multi chip package) m6mgb/t331s4bkt
|
